Aldec's Simulation Accelerator Leads PnpNetwork Technologies to Successful Tape Out
Henderson Nevada, May 20th, 2003 -- Aldec, Inc., a pioneer in mixed language simulation and advanced design tools for FPGA and ASIC devices, announced today design completion and successful tape out by PnpNetwork Technologies, Inc. utilizing Aldec's Riviera-IPT to accelerate the verification process. Riviera-IPT includes Aldec's industry-proven VHDL and Verilog mixed-language simulation kernel as well as the licensed hardware acceleration technology for ASIC and high-density FPGA designers for new generation system-on-chip designs.
PnpNetwork Technologies Design
PnpNetwork Technologies, Inc. successfully completed an ASIC core chip for a terrestrial reception set-top-box using Riviera-IPT to accelerate verification runs from days to hours during project development. The performance increase was primarily realized during the RTL debug stage, where many of the design's small iterations previously created the largest bottleneck for simulation times.
"We used to spend days simulating lots of test vectors; after implementing Aldec's hardware acceleration we were able to shorten this time to less than half an hour. Riviera-IPT was especially helpful when debugging because of the exorbitant time that's typically consumed during simulation," stated Younguk Oh, R&D Director for PnpNetwork Technologies, Inc., adding, "we found that Aldec's simulation accelerator enables us to settle various tests and debugging much faster and with better results."
Complete Verification Platform
Riviera-IPT's common kernel architecture supports VHDL, Verilog, SystemC™, assertions and acceleration. It also handles memories and devices such as DSPs and ASICs for joint verification of legacy designs, EDIF-based IP cores, existing hardware, and HDL blocks. By eliminating potential conflicts between verification tools, teams and design methods, Riviera-IPT is able to accelerate design verification by 10x-50x. Designers in turn save time and produce more reliable tapeouts.
Riviera-IPT enables designers to verify and optimize their designs in smaller-sized, more manageable blocks. Each block is verified in software by Riviera-IPT's built-in, event-driven simulator to allow for total visibility and debugging of the module before it is synthesized and placed in the hardware accelerator. After the verified module is placed in the hardware board, it remains "connected" to the remainder of the design residing in the software simulator, but eliminates the typical processing overhead. Ultimately, the majority of the design blocks, including assertions, reside in hardware, while the behavioral testbench and SystemC components remain in software. The interface between the components in hardware and software is managed through Riviera-IPT's Design Verification Manager (DVM), which facilitates the entire process and provides communication between the software and hardware components.
"With over 70% of the development cycle typically spent verifying the design at the functional level, Riviera-IPT has the ability to accelerate this process by 50x," stated Eric Seabrook, Product Marketing Manager for Aldec, adding, "we were very pleased with the performance gains PnpNetwork Technologies achieved using Riviera IPT."
System Configuration
Based on Aldec's industry-proven mixed HDL verification environment, Riviera-IPT includes an IEEE VHDL, Verilog and EDIF common kernel simulator, the Design Verification Manager (DVM), a hardware accelerator board with a capacity of up to 12 million FPGA gates, and an interface to a SystemC compiler. Optionally, Synplicity's Synplify™ logic synthesis may be added to complete the design flow. The Riviera-IPT system can be configured for UNIX, Linux or Windows NT/2000/XP. Riviera-IPT will accommodate up to 12 million FPGA gates or 3 million ASIC gates.
About Aldec
Aldec, Inc., a 19-year EDA tool provider, is committed to delivering high-performance, HDL-based design verification software for UNIX, Linux and Windows platforms. Aldec is dedicated and responsive to serving its customers' needs with its offices located around the globe. Continuous innovation, superior product quality and total commitment to customer service comprise the foundation of Aldec's strategic objectives. Additional information about Aldec is available at http://www.aldec.com.
About PnpNetwork Technologies, Inc.
PnpNetwork Technologies, Inc. is a fabless design company, providing CBI SOC and PnP Solutions. CBI SoC (Communication and Broadcasting Integration System on Chip) includes Channel Decoder ASSP for digital broadcasting receiver such as DVB-S/DSS (PN1010), DVB-T (PN2020), DAB (PN3030), DVB-C (PN4040) and PnP Solutions (Plug and Play System On Chip) consist of PnP SOC, Software and Evaluation Tool Kits to provide PnP DTV. Additional information about PnpNetwork Technologies, Inc. is available at: www.pnpnetwork.com
